of power at 1.4 GHz. The T1 is a new-from-the-ground-up SPARC microprocessor implementation that conforms to the UltraSPARC Architecture 2005 specification...
20 KB (2,698 words) - 22:55, 3 August 2024
Microsystems' UltraSPARC T2 microprocessor is a multithreading, multi-core CPU. It is a member of the SPARC family, and the successor to the UltraSPARC T1. The...
10 KB (1,331 words) - 10:19, 2 June 2024
The UltraSPARC II, code-named "Blackbird", is a microprocessor implementation of the SPARC V9 instruction set architecture (ISA) developed by Sun Microsystems...
5 KB (577 words) - 02:10, 7 September 2024
The UltraSPARC IV was developed as part of Sun's Throughput Computing initiative, which included the UltraSPARC V Millennium, Gemini and UltraSPARC T1 Niagara...
6 KB (554 words) - 03:16, 21 December 2021
Microsystems' Sun Fire and SPARC Enterprise product lines were based on early generations of CMT technology. The UltraSPARC T1 based Sun Fire T2000 and...
11 KB (759 words) - 16:39, 19 September 2024
The UltraSPARC III, code-named "Cheetah", is a microprocessor that implements the SPARC V9 instruction set architecture (ISA) developed by Sun Microsystems...
9 KB (1,238 words) - 17:30, 6 February 2024
component of the T-carrier system for telecommunication UltraSPARC T1, a microprocessor AYYA T1, a smartphone developed by Rostec as part of the Ayya (smartphone)...
5 KB (713 words) - 14:21, 14 October 2024
64-bit, 32-thread microprocessor, the UltraSPARC T1 processor. On March 21, 2006, Sun released the source code to the T1 IP core under the GNU General Public...
3 KB (250 words) - 04:51, 19 October 2024
the OpenSPARC T1 design. It is a single UltraSPARC V9 core capable of 4-way SMT. Like the T1, the source code is licensed under the GPL. OpenSPARC T2, released...
76 KB (6,263 words) - 21:09, 25 October 2024
exhibit CMP, including the x86-64 Opteron and Athlon 64 X2, the SPARC UltraSPARC T1, IBM POWER4 and POWER5, as well as several video game console CPUs...
100 KB (11,315 words) - 10:59, 12 November 2024