SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. SSSE3 was first introduced...
8 KB (445 words) - 03:43, 12 January 2024
SSE, SSE2, SSE3, SSSE3, Intel 64, XD bit (an NX bit implementation) Steppings: A1 All models support: MMX, SSE, SSE2, SSE3, SSSE3, Intel 64, XD bit (an...
150 KB (4,443 words) - 21:10, 23 June 2024
post-Diamondville Atom microprocessors. All models support: MMX, SSE, SSE2, SSE3, SSSE3, Intel 64, XD bit (an NX bit implementation), Hyper-Threading Transistors:...
86 KB (3,164 words) - 09:36, 25 July 2024
64-bit Core microarchitecture. All models support: MMX, SSE, SSE2, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit...
101 KB (3,933 words) - 09:25, 25 July 2024
and Core 7-branded processors. All models support: MMX, SSE, SSE2, SSE3, SSSE3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit...
469 KB (13,712 words) - 03:49, 22 August 2024
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation)...
36 KB (331 words) - 04:57, 29 January 2024
cores. Requires firmware support. Requires firmware support. No SSE4. No SSSE3. Single-precision performance is calculated from the base (or boost) core...
198 KB (11,293 words) - 06:35, 22 August 2024
All models support: MMX, Streaming SIMD Extensions (SSE), SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, Advanced Vector Extensions (AVX), Enhanced Intel SpeedStep...
34 KB (431 words) - 22:11, 10 August 2024
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX2, AVX-512, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an...
46 KB (648 words) - 12:09, 28 April 2024
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation)...
25 KB (336 words) - 20:09, 15 April 2024